This invention relates to a method for implanting ionized particles into a material and more specifically to a method particularly suited for manufacturing insulated gate field effect semiconductor devices.
Ion implanation is a well-known method utilized in semiconductor and other fabrication processes. In general, charged particles are utilized to introduce atoms or molecules into a substrate material. The substrate is typically a semiconductor wafer formed of silicon or other material common in semiconductor processing. The materials to be injected by ion inplantation are typical dopants such as boron or phosphor. The dopants add impurities to the substrate. The dopant to be implanted into the substrate is charged and accelerated towards the semiconductor by a high-voltage. The ion distribution on the surface of the substrate is generally uniform. The density and the depth of the implanted ions is a function of the acceleration voltage and the ion dose. After ions of the dopant have been implantated, the atoms and molecules are usually activated by an annealing process at an elevated temperature.
Ion implantation is particularly useful in the fabrication of metal-oxide semiconductors (MOS) and complementary metal-oxide semiconductors (CMOS). The fabrication of CMOS devices conveniently uses ion implantation because CMOS devices require a number of different doping steps and such steps are more successfully performed with ion implantation. For example, CMOS devices typically utilize a boron implantation for P wells, a boron implantation for P-channel threshold voltage adjustment, a phosphorous implantation for N-channel transistors, and a boron implantation for P-channel transistors. Typical steps for CMOS devices are shown in the article entitled "A Fully Plasma Etched Ion Implanted CMOS Process", By: A. Aitken, R. G. Poulsen, A. T. P. MacArthur, J. J. White, Technical Digest 1976 International Electron Device Meeting, Copyright 1976 by the Institute of Electrical and Electronics Engineers, Incorporated.
While such CMOS ion implantation techniques are well-known, there is a need for improved steps particularly where high density semiconductor devices are to be fabricated.
The trend in the semiconductor field, of course, is to fabricate a greater number of elements per unit of area. That trend demands that the dimensions of semiconductor elements become smaller and smaller. For example, the thickness of the gate oxide layers in CMOS devices is typically 500 angstroms or less. These small dimensions permit relatively low threshold voltages in MOS devices and hence are frequently desirable.
The use of ion implanation with such relatively thin gate oxide layers has resulted in fabrication problems. The ion implantation process is used to form source and drain regions within the substrate. A thin gate oxide layer covers the surface of the substrate above the area where the source and drain regions are to be formed. The ion implantation to form the source and drain regions occurs through the oxide layer. Frequently, a silicon gate mask is employed over the thin gate oxide layer to separate the source and drain regions. Ions incident on the mask are stopped by the silicon gate material and tend to create a high electrostatic field. That electrostatic field tends to cause a voltage potential across the thin gate oxide layer. The strength of the electrostatic field is a direct function of the ion dose and is typically in the order of 10.sup.4 volts/centimeter. Such a voltage is sufficiently high to cause dielectric breakdown of the gate oxide and hence causes damage to the thin gate oxide layer.
The problem of damage to the gate oxide layer during ion implantation both hinders the obtaining of high yields and/or the obtaining of high densities.
In view of the above background of the invention, it is the object of the present invention to provide a process for ion implantation which is particularly useful in manufacturing semiconductor devices, such as MOS and CMOS devices, without causing gate oxide damage.